By Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul
This monograph is predicated at the 3rd author's lectures on machine structure, given in the summertime semester 2013 at Saarland college, Germany. It incorporates a gate point development of a multi-core laptop with pipelined MIPS processor cores and a sequentially constant shared memory.
The publication comprises the 1st correctness proofs for either the gate point implementation of a multi-core processor and likewise of a cache established sequentially constant shared reminiscence. This opens the right way to the formal verification of synthesizable for multi-core processors within the future.
Constructions are in a gate point version and hence deterministic. by contrast the reference types opposed to which correctness is proven are nondeterministic. the advance of the extra equipment for those proofs and the correctness facts of the shared reminiscence on the gate point are the most technical contributions of this work.
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This monograph relies at the 3rd author's lectures on computing device structure, given in the summertime semester 2013 at Saarland collage, Germany. It encompasses a gate point building of a multi-core desktop with pipelined MIPS processor cores and a sequentially constant shared reminiscence. The ebook includes the 1st correctness proofs for either the gate point implementation of a multi-core processor and in addition of a cache established sequentially constant shared reminiscence.
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Extra info for A Pipelined Multi-core MIPS Machine Hardware Implementation and Correctness Proof
Eni )(a) = fi (e1 (a), . . , eni (a)) . The following small example shows that this very formal and detailed set of rules captures our usual way of evaluating expressions: (x1 ∧ x2 )(0, 1) = x1 (0, 1) ∧ x2 (0, 1) = 0∧1 =0. Boolean equations, therefore, are written as e=e , where e and e are expressions involving variables x = x[1 : n]. They come in two ﬂavors: • Identities. An equation e = e is an identity iﬀ for any substitution of the variables a = a[1 : n] ∈ Bn , expressions e and e evaluate to the same value in B: ∀a ∈ Bn : e(a) = e (a) .
2 Some Basic Circuits a a n n ∨ n-Zero 1 zero 37 nzero 1 nzero zero (a) symbol (b) implementation Fig. 12. n-bit zero tester a a b b n n n n n n-eq 1 n-Zero 1 eq neq 1 eq (a) symbol 1 neq (b) implementation Fig. 13. n-bit equality tester The inputs a[n − 1 : 0], b[n − 1 : 0] and outputs eq, neq of an n-bit equality tester in Fig. 13 satisfy eq ≡ a = b , neq ≡ a = b . The implementation uses neq(a[n − 1 : 0]) = nzero(a[n − 1 : 0] ⊕ b[n − 1 : 0]) , eq = neq . An n-decoder is a circuit with inputs x[n − 1 : 0] and outputs y[2n − 1 : 0] satisfying ∀i : yi = 1 ↔ x = i .
For the induction base c = −1 and the signals coming from the registers x[i] with d(x[i]) = 0, we have tmin(x[i]) = ρ ∧ tmax(x[i]) = σ . 6. For part 2 there is nothing to show. 3 Clocked Circuits 53 For the induction step we go from c to c + 1 and ﬁrst show part 2 of the lemma. Consider Fig. 25. For register inputs y = x[i]in and clock enable signals y = x[i]ce we have from the induction hypothesis: ∀t ∈ [e(c) + tmax(y), e(c + 1) + tmin(y)] : y(t) = y c . From the lemma’s assumptions we get for all y = x[i]in, y = x[i]ce ∀y : th ≤ tmin(y) ∧ tmax(y) + ts ≤ τ , which implies e(c) + tmax(y) ≤ e(c) + τ − ts = e(c + 1) − ts, e(c + 1) + tmin(y) ≥ e(c + 1) + th .